In various integrated circuit applications it is necessary for a logic circuit operating with relatively low logic levels to drive another logic circuit operating at higher logic levels. For certain complementary metal oxide semiconductor (CMOS) applications, for example, it is often necessary to translate 0-2.5 V logic signals generated by one logic circuit (i.e., 0 V for logic LOW and 2.5 V for logic HIGH) to 0-3.3 V logic signals to be supplied to another logic circuit operating at the higher levels. Accordingly, output buffer circuits have been developed to achieve such translation.
One prior art output buffer is shown in FIG. 1. Buffer circuit 10 operates to translate an input logic signal "All" at terminal 12, e.g., 0-2.5 V logic, to a logic signal "Z" at output terminal 14, e.g., 0-3.3 V logic. Transistors P1-P4 are p-channel field effect transistors, i.e. p-FETS (depicted with circles at their gates and outwardly pointing arrows), whereas devices N1-N4 are n-channel FETS (n-FETS). A supply voltage VDD1 of 3.3 V is applied to the drains of transistors P2-P4, and a supply voltage B. Morris 24 (90-D04) VDD2 of 2.5 V is applied to the drain of FET P1. Input logic signal A is applied to the gates of FETS N1 and N3. When the input A is zero volts (logic LOW) with respect to reference potential VSS, the output Z is also 0 V, whereas when voltage A is 2.5 V, the output Z is 3.3 V. Due to tolerance variation, the logic HIGH output signal Z may be as high as 3.6 V.
Transistors P1 and N1 form a standard inverter 18 to produce inverted voltage A.sub.n at node 15 which is the complement of voltage A. Transistors P2, P3, N2 and N3 form a cross-coupled pair. The sources of FETS N1, N2 and N3 are each tied to reference potential VSS (e.g., ground). When signal A is LOW, signal A.sub.N is HIGH, FET N2 is ON and FET N3 is OFF. This forces node 13 LOW, turning on FET P3, which pulls node 16 up to nearly VDD1. FET N4 is thus ON, while FET P4 is OFF, whereby the output signal Z is LOW. For this condition, transistor N3 has almost the full value of VDD1 (up to 3.6 V) across its drain-to-source terminals. Likewise, when input level A is HIGH (2.5 V), the output Z is nearly equal to VDD1 so that transistor N4 must tolerate a drain-to-source voltage (VDS) of up to 3.6 V. Transistor N2 must also tolerate this high V.sub.DS voltage for the latter condition.
In some CMOS technologies, the p-FET can tolerate a higher source-to-drain voltage than the n-FET can tolerate from drain-to-source. For instance, in one specific 0.25 .mu.m (device length), 2.5 V technology, both the p-FET and the n-FET can typically tolerate up to 3.6 V across their gate oxides, the p-FET can tolerate a source-to-drain voltage of 3.6 V, but the n-FET can only tolerate up to 2.7 V from drain-to-source. To increase the drain-to-source voltage tolerance for the n-FETs, an additional mask level may be added which tailors the doping levels in the n-channel. Thus, in buffer 10 of FIG. 1, n-FETS N2-N4 are typically devices which have been fabricated using such an additional mask level since they are required to tolerate a V.sub.DS voltage of up to 3.6 V as discussed above. The additional processing step for this mask level, however, increases the fabrication cost and throughput time for the wafers.